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| 1 | Mirror image:newfangled cell-level layout technique for single-event transient mitigation显示文摘Recent years,the hardening of combinational circuits is becoming a common concern.Unlike the transistor-level hardening technique,the cell-level hardening technique,a divide and conquer strategy,can substantially make use of some typical character in the cell-circuit module to mitigate single event transient(SET)sensitivity.The mirror image(MI)technique proposed in this paper can adequately enhance the charge sharing in those cell-circuits with stage-by-stage inverter-like structure.3D TCAD mixed-mode simulation have been performed in 65 nm twinwell bulk CMOS process,the results indicate that the MI technique can almost reduce the SET pulse width from the anterior-stage PMOS over 25%,and can mitigate the SET pulse width from the posterior-stage PMOS about 10%.The MI technique,a represent of the cell-level technique,may be the future of the hardening of combinational circuits. | Pengcheng Huang Shuming Chen Zhengfa Liang Jianjun Chen Chunmei Hu Yibai He | 2014 | Chinese Science Bulletin2014，59，23： | 4 |
| 2 | Simulation study of N-hit SET variation in differential cascade voltage switch logical circuits显示文摘The advancement in the process leads to more concern about the Single Event(SE) sensitivity of the Differential Cascade Voltage Switch Logic(DCVSL) circuits. The simulation results indicate that the Single Event Transient(SET) generated at the DCVSL gate is much larger than that at the ordinary CMOS gate, and their SET variation is different. Based on charge collection, in this paper, the effective collection time theory is proposed to set forth the SET pulse generated at the DCVSL gate. Through 3D TCAD mixed-mode simulation in 65 nm twin-well bulk CMOS process, the effects on SET variation of device parameters such as well contact size and environment parameters such as voltage are investigated. | HUANG PengCheng CHEN ShuMing CHEN JianJun WU ZhenYu LIANG ZhengFa HU ChunMei LIANG Bin LIU BiWei | 2015 | Science China(Information Sciences)2015，58，2： | 1 |
| 3 | Experimental characterization of the bipolar effect on P-hit single-event transients in 65 nm twin-well and triple-well CMOS technologies显示文摘Single-event charge collection is controlled by drift, diffusion and the bipolar effect. Previous work has established that the bipolar effect is significant in the p-type metal-oxide-semiconductor field-effect transistor(PMOS) in 90 nm technology and above. However, the consequences of the bipolar effect on P-hit single-event transients have still not completely been characterized in 65 nm technology. In this paper, characterization of the consequences of the bipolar effect on P-hit single-event transients is performed by heavy ion experiments in both 65 nm twin-well and triple-well complementary metal-oxide-semiconductor(CMOS) technologies. Two inverter chains with clever layout structures are explored for the characterization. Ge(linear energy transfer(LET) = 37.4 Me V cm^2/mg) and Ti(LET = 22.2 Me V cm^2/mg) particles are also employed. The experimental results show that with Ge(Ti) exposure, the average pulse reduction is 49 ps(45 ps) in triple-well CMOS technology and 42 ps(32 ps) in twin-well CMOS technology when the bipolar effect is efficiently mitigated. This characterization will provide an important reference for radiation hardening integrated circuit design. | CHEN JianJun LIANG Bin CHI YaQing | 2016 | Science China(Technological Sciences)2016，59，3： | 1 |
| 4 | 一种选择单粒子瞬态脉冲敏感结点的方法显示文摘逻辑电路中NMOS管或者PMOS管受到高能粒子撞击,会产生单粒子瞬态脉冲错误。针对这种现象,提出一种识别和选择电路中敏感结点的新方法,并与门的逻辑掩蔽效应加权综合考虑,对所选择的结点通过增大恢复管的尺寸来加固,以减小单粒子效应导致的软错误率。 | 宋依青 严佳倩 | 2018 | 常州工学院学报2018，31，2： | 0 |
| 5 | Single event upset induced by single event double transient and its well-structure dependency in 65-nm bulk CMOS technology显示文摘Single event upset (SEU) is one of the most important origins of soft errors in aerospace applications.As technology scales down persistently, charge sharing is playing a more and more significant effect on SEU of flip-flop. Charge sharing can often bring about multi-node charge collection in storage nodes and non-storage nodes in a flip-flop. In this paper, multi-node charge collection in flip-flop data input and flip-flop clock signal is investigated by 3D TCAD mixed-mode simulations, and the simulate results indicate that single event double transient (SEDT) in flip-flop data input and flip-flop clock signal can also cause a SEU in flip-flop. This novel mechanism is called the SEDT-induced SEU, and it is also verified by heavy-ion experiment in 65 nm twin-well process. The simulation results also indicate that this mechanism is closely related with the well-structure,and the triple-well structure is more effective to increase the SEU threshold of this mechanism than twin-well structure. | Pengcheng HUANG Shuming CHEN Jianjun CHEN | 2016 | Science China(Information Sciences)2016，59，4： | 0 |
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