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| 1 | Analysis of process variations impact on the single-event transient quenching in 65 nm CMOS combinational circuits显示文摘Single-event transient pulse quenching(Quenching effect)is employed to effectively mitigate WSET(SET pulse width).It enhanced along with the increased charge sharing which is norm for future advanced technologies.As technology scales,parameter variation is another serious issue that significantly affects circuit’s performance and single-event response.Monte Carlo simulations combined with TCAD(Technology Computer-Aided Design)simulations are conducted on a six-stage inverter chain to identify and quantify the impact of charge sharing and parameter variation on pulse quenching.Studies show that charge sharing induce a wider WSET spread range.The difference of WSET range between no quenching and quenching is smaller in NMOS(N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor)simulation than that in PMOS’(P-Channel Metal-Oxide-Semiconductor Field-Effect Transistor),so that from parameter variation view,quenching is beneficial in PMOS SET mitigation.The individual parameter analysis indicates that gate oxide thickness(TOXE)and channel length variation(XL)mostly affect SET response of combinational circuits.They bring 14.58%and 19.73%average WSET difference probabilities for no-quenching cases,and 105.56%and 123.32%for quenching cases. | WANG TianQi XIAO LiYi ZHOU Bin QI ChunHua | 2014 | Science China(Technological Sciences)2014，57，2： | 2 |
| 2 | Ethnopharmacologic study of Chinese rhubarb显示文摘 | Xiao Peigen He Liyi Wang Liwei | 1984 | J Ethnopharmacol1984，10，3： | 1 |
| 3 | CORDIC-Based Unified Architectures for Computation of DCT/IDCT/DST/IDST显示文摘 | Hai Huang Liyi Xiao Jiaming Liu | 2014 | Circuits, Systems, and Signal Processing2014，，： | 1 |
| 4 | Enhanced memory reliability against multiple cellupsets using decimal matrix code 显示文摘 | GUO Jing XIAO Liyi MAO Zhigang | 2014 | IEEE TransVLSI Syst2014，22，1： | 1 |
| 5 | Single-event upset prediction in static random access memory cell account for parameter variations显示文摘Dear editor,As technology downscales, the impact of process variations (PVs) becomes a harmful problem,which significantly affects the integrated circuit(IC) performance (1)The transistor parameters can be significantly affected by the lithography,random dopant fluctuations (RDFs), surface-state charge, gate depletion, and line edge roughness[1, 2]. | Mingxue HUO Guoliang MA Bin ZHOU Liyi XIAO Chunhua QI Yanqing ZHANG Jianning MA Yinghun PIAO Tianqi WANG | 2019 | Science China(Information Sciences)2019，62，6： | 0 |
| 6 | Design of a high-performance 12T SRAM cell for single event upset tolerance显示文摘Dear editor,As an important part of a cache, static random-access memory(SRAM) has been extensively utilized to satisfy the application requirements in modern embedded processors.It plays an important role in data interaction between the central processing unit and internal memory. Moreover,these data interactions are safety critical requiring highly reliable SRAM. However, owing to complementary metaloxide-semiconductor(CMOS) manufacturing processes entering the nanoscale era, SRAM is increasingly vulnerable to a single event upset(SEU). | Chunhua QI Yanqing ZHANG Guoliang MA Chaoming LIU Tianqi WANG Liyi XIAO Mingxue HUO Guofu ZHAI | 2021 | Science China(Information Sciences)2021，64，11： | 0 |
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