3篇
您的检索式：作者名="Neeta Pandey"
|
|
|
题名
|
作者
|
年代
|
出处
|
被引量
|
| 1 | A boosted negative bit-line SRAM with write-assisted cell in 45 nm CMOS technology显示文摘A new 11 T SRAM cell with write-assist is proposed to improve operation at low supply voltage. In this technique, a negative bit-line voltage is applied to one of the write bit-lines, while a boosted voltage is applied to the other write bit-line where transmission gate access is used in proposed 11 T cell. Supply voltage to one of the inverters is interrupted to weaken the feedback. Improved write feature is attributed to strengthened write access devices and weakened feedback loop of cell at the same time. Amount of boosting required for write performance improvement is also reduced due to feedback weakening, solving the persistent problem of half-selected cells and reliability reduction of access devices with the other suggested boosted and negative bit-line techniques. The proposed design improves write time by 79%, 63% and slower by 52% with respect to LP 10 T, WRE 8 T and 6 T cells respectively. It is found that write margin for the proposed cell is improved by about 4×, 2.4× and 5.37× compared to WRE8 T, LP10 T and 6 T respectively. The proposed cell with boosted negative bit line(BNBL) provides47%, 31%, and 68.4% improvement in write margin with respect to no write-assist, negative bit line(NBL) and boosted bit line(BBL) write-assist respectively. Also, new sensing circuit with replica bit-line is proposed to give a more precise timing of applying boosted voltages for improved results. All simulations are done on TSMC 45 nm CMOS technology. | Vipul Bhatnagar Pradeep Kumar Neeta Pandey Sujata Pandey | 2018 | Journal of Semiconductors2018，39，2： | 1 |
| 2 | Real Time Control System for Metro Railways Using PLC & SCADA显示文摘This paper proposes to adopt SCADA and PLC technology for the improvement of the performance of real time signaling&train control systems in metro railways.The main concern of this paper is to minimize the failure in automated metro railways system operator and integrate the information coming from Operational Control Centre(OCC),traction SCADA system,traction power control,and power supply system.This work presents a simulated prototype of an automated metro train system operator that uses PLC and SCADA for the real time monitoring and control of the metro railway systems.Here,SCADA is used for the visualization of an automated process operation and then the whole opera-tion is regulated with the help of PLC.The PLC used in this process is OMRON(NX1P2-9024DT1)and OMRON’s Sysmac studio programming software is used for developing the ladder logic of PLC.The metro railways system has deployed infrastructure based on SCADA from the power supply system,and each station’s traction power control is connected to the OCC remotely which commands all of the stations and has the highest command priority.An alarm is triggered in the event of an emergency or system congestion.This proposed system overcomes the drawbacks of the current centralized automatic train control(CATC)system.This system provides prominent benefits like augmenting services which may enhance a network’s full load capacity and networkflexibility,which help in easy modification in the existing program at any time. | Ishu Tomar Indu Sreedevi Neeta Pandey | 2023 | Intelligent Automation & Soft Computing2023，，2： | 0 |
| 3 | A dual V_t disturb-free subthreshold SRAM with write-assist and read isolation显示文摘This paper presents a new dual V_t 8 T SRAM cell having single bit-line read and write, in addition to Write Assist and Read Isolation(WARI). Also a faster write back scheme is proposed for the half selected cells. A high V_t device is used for interrupting the supply to one of the inverters for weakening the feedback loop for assisted write. The proposed cell provides an improved read static noise margin(RSNM) due to the bit-line isolation during the read. Static noise margins for data read(RSNM), write(WSNM), read delay, write delay, data retention voltage(DRV), leakage and average powers have been calculated. The proposed cell was found to operate properly at a supply voltage as small as 0.41 V. A new write back scheme has been suggested for half-selected cells,which uses a single NMOS access device and provides reduced delay, pulse timing hardware requirements and power consumption. The proposed new WARI 8 T cell shows better performance in terms of easier write, improved read noise margin, reduced leakage power, and less delay as compared to the existing schemes that have been available so far. It was also observed that with proper adjustment of the cell ratio the supply voltage can further be reduced to 0.2 V. | Vipul Bhatnagar Pradeep Kumar Neeta Pandey Sujata Pandey | 2018 | Journal of Semiconductors2018，39，2： | 0 |
您所在的机构暂未开通此部分的功能，请联系管理员