| 1 | Integrating advanced reasoning into a SAT solver显示文摘In this paper, we present a SAT solver based on the combination of DPLL (Davis Putnam Logemann and Loveland) algorithm and Failed Literal Detection (FLD), one of the advanced reasoning techniques. We propose a Dynamic Filtering method that consists of two restriction rules for FLD: internal and external filtering. The method reduces the number of tested literals in FLD and its computational time while maintaining the ability to find most of the failed literals in each decision level. Unlike the pre-defined criteria, literals are removed dynamically in our approach. In this way, our FLD can adapt itself to different real-life benchmarks. Many useless tests are therefore avoided and as a consequence it makes FLD fast. Some other static restrictions are also added to further improve the efficiency of FLD. Experiments show that our optimized FLD is much more efficient than other advanced reasoning techniques. | DINGMin TANGPushan ZHOUDian | 2005 | Science in China(Series F)2005，48，3： | 2 |
| 2 | High—Speed Clock Tree Simulation with Fast Wavelet Collocation Method显示文摘In this paper, we propose a fast wavelet collocation algorithm for high-speed clock tree simulation.Taking advantage of the specific structure of clock trees and the superior computational property of wavelets, the proposed algorithm presents the following merits: (1) It can perform both transient simulation and steady-state analysis with arbitrary input; (2) It employs nonlinear buffer model and nonuniform interconnect wire model; (3)It has a low computational complexity O(N) and can deal with considerably large circuits; (4) The Fast Wavelet Col-location Method works in time domain so that the simula-tion error in time domain can be well-controlled. Numer-ical experimental results demonstrate the promising fea-tures of the proposed algorithm in high-speed clock tree simulations. | LIXin ZENGXuan SHIJianlei CHENWenbin ZHOUDian LINGXieting | 2003 | Chinese Journal of Electronics2003，12，2： | 0 |
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