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| 1 | A low-jitter PLL clock generator for microprocessor with lock range of 340-612 MHz 显示文摘 | BOERSTLER D W | 1999 | IEEE J SSC1999，34，4： | 1 |
| 2 | Silicon-micromachined microchannel plates显示文摘 | Beetz C P Boerstler R Steinbeck J | | 0，，： | 1 |
| 3 | A low-jitter dock generator for microprocessors with lock range of 340-612 MHz显示文摘 | Boerstler D W | 1999 | IEEE JSSC1999，34，4： | 1 |
| 4 | Silicon-micromachined microchannel plates显示文摘 | BEETZ C P BOERSTLER R W STEINBECK J | 2000 | Nuclear Instruments and Methods in Physics Research A2000，442，： | 1 |
| 5 | Governmental incentives for corporate self-regulation显示文摘 | John C Ruhnka and Heidi Boerstler | 1998 | Journal of Business Ethics1998，17，： | 1 |
| 6 | Silicon-micromachined microchannel plates 显示文摘 | CP Beetz R Boerstler J Steinbeck | 2000 | Nuclear Instruments and Methods in Physics Research A(S0168-9002)2000，442，： | 1 |
| 7 | Overview of the architecture,circuit design,and physical implementation of a firstgeneration Cell processor显示文摘 | Pham D C Aipperspach T Boerstler D | 2006 | IEEE Journal2006，41，： | 1 |
| 8 | A Low - Jitter PLL Clock Generator for Microp rocessor with Lock Range of 340-612 MHz显示文摘 | Boerstler D W | 1999 | IEEE Journal of Solid - State Circuits1999，34，04： | 1 |
| 9 | Si microchannel plates for image intensification 显示文摘 | SMITH A W BEETZ C P BOERSTLER R W | 2000 | SPIE2000，4128，： | 1 |
| 10 | A Lowe-Jitter PLL Clock Generator for Microprocessor with Lock Range of 340-612MHz显示文摘 | David W Boerstler | 1999 | IEEE Journal of Solid-State Circuits1999，34，4： | 1 |
| 11 | Overview of the Architecture,Circuit Design,and Physical Implementation of a First-Generation Cell Processor显示文摘 | Pham D C Boerstler T Bolliger D | 2006 | IEEE Journal of Solid-State Circuits2006，41，1： | 1 |
| 12 | Silicon-micromachined microchannel plates 显示文摘 | BEETZ C P BOERSTLER R STEINBECK J | 2000 | Nuclear Instruments and Methods in Physics Research: A2000，442，： | 1 |
| 13 | Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor显示文摘 | Pham D C Aipperapach T Boerstler D | 2006 | IEEE Journal of Solid- State Circuits2006，41，1： | 1 |
| 14 | Consumer response to marketplace deception: Implication of the persuasion knowledge model显示文摘 | Xie G X Boush D M and Boerstler C N | 2007 | Advances in Consumer Research2007，34，： | 1 |
| 15 | Si microchannel plates for image intensification显示文摘 | BEETZ C P BOERSTLER R W BOERSTLER J W | 2000 | SPIE2000，4128，： | 1 |
| 16 | Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor显示文摘 | PHAM D AIPPERSPACH T BOERSTLER D | 2006 | IEEE JSSC2006，41，1： | 1 |
| 17 | Overview of the architecture, circuit design, and physical implementation of a first-generation Cell processor 显示文摘 | Dac C Pham Tony Aipperspach David Boerstler | 2006 | IEEE Journal of Solid-State Circuits2006，41，1： | 1 |
| 18 | Governmentalincentives for corporate self-regulation显示文摘 | Ruhnka J C and Boerstler H | 1998 | Journal of Business Ethics1998，17，： | 1 |
| 19 | A low-jitter PLL clock generator for microprocessors with lock range of 340 - 612 MHz 显示文摘 | BOERSTLER D W | 1999 | IEEE J Sol Sta Circ1999，34，4： | 1 |
| 20 | Silicon - micromachined microchannel plates 显示文摘 | Charles P Beetz Robert Boerstler John Steinbeck | 2000 | Nuclear Instruments and Methods in Physics Research2000，442，： | 1 |
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