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| 1 | A high speed 1000 fps CMOS image sensor with low noise global shutter pixels显示文摘A low read noise 8T global shutter pixel for high speed CMOS image sensor is proposed in this paper.The pixel has a pixel level sample-and-hold circuit and an in-pixel amplifier whose gain is larger than one.Using pixel level sample-and-hold circuit,the KTC noise on FD node can be effectively cancelled by correlated double sampling operation.The in-pixel amplifier with a gain larger than one is employed for reducing the pixel level sample-and-hold capacitors thermal noise and their geometric size.A high speed 1000 fps 256×256 CMOS image sensor based on the pixel is implemented in 0.18μm CMOS process.The chip active area is 5 mm×7 mm with a pixel size of 14μm×14μm.The developed sensor achieves a read noise level as low as 14.8e-while attaining a high fill factor of 40%.The full well capacity can contain 30840e-and the resulting signal dynamic range is 66 dB. | ZHOU YangFan CAO ZhongXiang QIN Qi LI QuanLiang SHI Cong WU NanJian | 2014 | Science China(Information Sciences)2014，57，4： | 8 |
| 2 | High-speed visual target tracking with mixed rotation invariant description and skipping searching显示文摘This paper proposes a novel high-speed visual target tracking system based on mixed rotation invariant description(MRID) and skipping searching method. MRID is a novel rotation invariant description of texture and edge information by annular histograms and dominant direction. It overcomes rotation variant and large computation issues in conventional LBP-HOG feature description. The skipping searching method used in tracking can remarkably decrease the computation time by avoiding repeated searching operations.The proposed tracking system contains an image sensor, a hierarchical vision processor and an actuator with2 dimensions of freedom(DOF). The vision processor integrates processors with pixel-and row-level parallelism to speed up the tracking algorithm. Experiment results show that the proposed system can achieve over 1000-fps processing speed of the tracking algorithm under 750 × 480 resolution image. | Yongxing YANG Jie YANG Zhongxing ZHANG Liyuan LIU Nanjian WU | 2017 | Science China(Information Sciences)2017，60，6： | 5 |
| 3 | A low power global shutter pixel with extended FD voltage swing range for large format high speed CMOS image sensor显示文摘A low power 8T global shutter pixel with extended FD voltage swing range is proposed for large format high speed CMOS image sensor. The pixel has a negative threshold reset transistor, two in-pixel source followers, and a sample-and-hold circuit. The in-pixel first source follower is employed for reducing the pixel average current and maximum transient current. The negative threshold reset transistor is applied to extend the voltage swing of FD. Using pixel level sample-and-hold circuit, the k TC noise on FD node can be effectively nullified by correlated double sampling operation. A high speed 1000 fps 256×256 CMOS image sensor is implemented in 0.18 μm CMOS process. Two 10-bit cyclic ADC arrays are integrated in this prototype sensor chip. The active area of the chip is 10 mm×7 mm with a pixel size of 14 μm×14 μm. The developed sensor achieves an average current of 23 n A per pixel, a maximum transit current per pixel as low as 1113 n A, and a large FD voltage swing of 1.78 V. The sensor temporal noise level is 103 e-and full well capacity has 27000 e-which results in 48.3 d B signal dynamic range. | ZHOU YangFan CAO ZhongXiang HAN Ye LI QuanLiang SHI Cong DOU RunJiang QIN Qi LIU Jian WU NanJian | 2015 | Science China(Information Sciences)2015，58，4： | 4 |
| 4 | A 256×256 time-of-flight image sensor based on center-tap demodulation pixel structure显示文摘This paper proposes a 256×256 time-of-flight(TOF) image sensor based on the center-tap(CT)demodulation pixel structure. The image sensor can capture both the two-dimensional(2D) high speed image and the three-dimensional(3D) depth image. The CT pixel consists of two split pinned photodiode(PPD)regions and two pairs of transfer transistors. The transfer transistors adopt a non-uniform doped channel(NUDC) structure, which can increase the electron transfer speed along the transfer channel and eliminate the image lag for high speed imaging. The pixel size is 10 μm×10 μm, and we design the implementation process of the pixel to increase the electron transfer speed. The sensor is fabricated in a 0.18 μm 1P5 M CMOS image sensor process. Test results show that it can capture the 430-fps intensity image and the 90-fps depth image in two different imaging modes. The rectified non-linearity within the 1.0–7.5 m depth measurement range achieves less than 3 cm, and the measurement accuracy achieves 4.0 cm at 2.5 m, corresponding to the relative error of1.6%. | Zhe CHEN Shan DI Zhongxiang CAO Qi QIN Fei JI Liyuan LIU Nanjian WU | 2016 | Science China(Information Sciences)2016，59，4： | 4 |
| 5 | A 2.4 GHz low power CMOS transceiver for LR-WPAN applications显示文摘A 2.4 GHz low power transceiver for low-rate wireless personal area network(LR-WPAN)applications is presented.The optimized low-IF receiver consists of a novel current reuse RF front-end with an inductor-less-load balun LNA and quadrature mixer,and an adaptive analog baseband to reduce power and area.It achieves-94 dBm of sensitivity,-9 dBm of IIP3 and 28 dBc of image rejection.The phase-locked loop based direct phase modulated transmitter is proposed to reduce power and deliver a+3 dBm output power.The phase noise of the low power frequency synthesizer with current reuse stacked LC-VCO achieves-107.8 dBc/Hz at 1 MHz offset.An ultra-low power nonvolatile memory is used to store configuration data and save power.The chip is implemented in a 0.18μm CMOS process,and the area is less than 2.8 mm2.The transceiver consumes only 10.98 mW in the receiving mode and 13.32 mW in the transmitting mode. | LIU WeiYang CHEN JingJing LIU XiaoDong WANG HaiYong WU NanJian | 2014 | Science China(Information Sciences)2014，57，8： | 3 |
| 6 | Neuromorphic vision chips显示文摘The paper reviews the progress of neuromorphic vision chip research in decades. It focuses on two kinds of the neuromorphic vision chips: frame-driven(FD) and event-driven(ED) vision chips. The FD and ED vision chips are very different from each other in system architecture, image sensing, image information coding, image processing algorithm, design methodology. The vision chips can overcome serial data transmission and processing bottlenecks in traditional image processing systems. They can perform the high speed image capture and real-time image processing operations. This paper selects two typical chips from the two kinds of vision chips, respectively, and introduces their architectures, image sensing schemes, image processing processors and system operation. The FD neuromorphic reconfigurable vision chip comprises a high speed image sensor, a processing element array and self-organizing map neural network. The FD vision chip has the advantages in image resolution, static object detection, time-multiplex image processing, and chip area. The ED neuromorphic vision chip system is based on address-event-representation image sensor and event-driven multi-kernel convolution network. The ED vision chip has the advantages in fast sensing, low communication bandwidth, brain-like processing, and high energy efficiency. Finally, this paper discusses the architecture and the challenges of the future neuromorphic vision chip and indicates that the reconfigurable vision chip with left-and right-brain functions integrated in the three dimensional(3 D) large-scale integrated circuit(LSI) technology becomes a trend of the research on the vision chip. | Nanjian WU | 2018 | Science China(Information Sciences)2018，61，6： | 2 |
| 7 | A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits显示文摘This paper proposes a synthesized injection-locked bang-bang phased-locked loop(SILBBPLL)with high digital controlled oscillator(DCO) frequency resolution. The SILBBPLL is expressed with hardware description language and automatically placed & routed(APR) by using standard digital circuit design flow. As the mismatch issues of the circuits are not considered carefully during the APR design flow, the phase noise performance is severely deteriorated. We adopt pulse injection locking technique to improve the phase noise performance. The DCO frequency resolution is critical for reducing the reference spur in a digital injection-locked PLL. Therefore, we propose novel frequency tuning circuits to increase the DCO frequency resolution so that the reference spurs are reduced. The frequency tuning circuits consist of a standard cell based high-linearity output feedback DAC(OFDAC) and two custom varactors. The OFDAC is used to tune the frequency of the DCO with the custom varactor precisely. The custom varactor is firstly designed,added into the standard cell library, and APR with the standard cells. The SILBBPLL chip with a core area of 0.008 mm^2 is implemented in 65 nm CMOS process. When operating at 1.8 GHz, the measured results show that the root-mean-square(RMS) jitter integrated from 10 kH z to 100 MHz is 1.1 ps, and the power consumption is 1.5 mW with a 0.8-V supply. The proposed SILBBPLL achieves a figure-of-merit(FoM) of -237.4 dB and a reference spur of -50.9 dBc. | Jincheng YANG Zhao ZHANG Nan QI Liyuan LIU Jian LIU Nanjian WU | 2019 | Science China(Information Sciences)2019，62，6： | 1 |
| 8 | High-speed target tracking system based on multi-interconnection heterogeneous processor and multi-descriptor algorithm显示文摘Dear editor,Target tracking has been a subject of intense scholarly research in past decades. Many parallel processors [1–4] and efficient tracking algorithms based on feature extraction [3–5] have been proposed to meet the requirements of high-speed tracking. However. | Jiaqing WANG Yongxing YANG Liyuan LIU Nanjian WU | 2019 | Science China(Information Sciences)2019，62，6： | 1 |
| 9 | A massively parallel keypoint detection and description(MP-KDD) algorithm for high-speed vision chip显示文摘This paper proposes a massively parallel keypoint detection and description(MP-KDD) algorithm for the vision chip with parallel array processors. The MP-KDD algorithm largely reduces the computational overhead by removing all floating-point and multiplication operations while preserving the currently popular SIFT and SURF algorithm essence. The MP-KDD algorithm can be directly and effectively mapped onto the pixel-parallel and row-parallel array processors of the vision chip. The vision chip architecture is also enhanced to realize direct memory access(DMA) and random access to array processors so that the MP-KDD algorithm can be executed more effectively. An FPGA-based vision chip prototype is implemented to test and evaluate our MP-KDD algorithm. Its image processing speed reaches 600–760 fps with high accuracy for complex vision applications, such as scene recognition. | SHI Cong YANG Jie LIU LiYuan WU NanJian WANG ZhiHua | 2014 | Science China(Information Sciences)2014，57，10： | 1 |
| 10 | Passive and semipassive wireless temperature and humidity sensors based on EPC generation-2 UHF protocol显示文摘 | Yu Shuangming Feng Peng Wu Nanjian | 2015 | IEEE Sensors Journal2015，15，4： | 1 |
| 11 | Novel Hybrid Voltage Controlled Ring Oscillators Using Single Electron and MOS Transistors 显示文摘 | ZHANG Wancheng WU Nanjian | 2007 | IEEE Trarns On Narzotechnology2007，6，2： | 1 |
| 12 | A high speed multi-level-parallel array processor for vision chips显示文摘This paper proposes a high speed multi-level-parallel array processor for programmable vision chips.This processor includes 2-D pixel-parallel processing element(PE)array and 1-D row-parallel row processor(RP)array.The two arrays both operate in a single-instruction multiple-data(SIMD)fashion and share a common instruction decoder.The sizes of the arrays are scalable according to dedicated applications.In PE array,each PE can communicate not only with its nearest neighbor PEs,but also with the next near neighbor PEs in diagonal directions.This connection can help to speed up local operations in low-level image processing.On the other hand,global operations in mid-level processing are accelerated by the skipping chain and binary boosters in RP array.The array processor was implemented on an FPGA device,and was successfully tested for various algorithms,including real-time face detection based on PPED algorithm.The results show that the image processing speed of proposed processor is much higher than that of the state-of-the-arts digital vision chips. | SHI Cong YANG Jie WU NanJian WANG ZhiHua | 2014 | Science China(Information Sciences)2014，57，6： | 1 |
| 13 | Terahertz detector for imaging in 180-nm standard CMOS process显示文摘A CMOS terahertz(THz) detector implemented in a 180-nm standard CMOS process is proposed,and room-temperature detection of 0.94-THz radiation is demonstrated. The detector consists of an integrated on-chip patch antenna and a source-feeding NMOS transistor as the rectifying element. To improve the power transfer efficiency between the patch antenna and NMOS transistor, a novel short-stub matching network is proposed. An open quarter-wavelength microstrip transmission line connecting gate is proposed to eliminate the influence of the bonding wire and pad on the antenna-transistor impedance matching. Illuminated by a 0.94-THz BWO source, the measured voltage responsivity(Rv) and noise equivalent power(NEP) of the detector are 31 V/W and 1.1 n W/Hz1/2, respectively. | Zhaoyang LIU Liyuan LIU Zhao ZHANG Jian LIU Nanjian WU | 2017 | Science China(Information Sciences)2017，60，8： | 1 |
| 14 | Exploration of high-speed 3.0 THz imaging with a 65 nm CMOS process显示文摘This paper describes a promising route for the exploration and development of 3.0 THz sensing and imaging with FET-based power detectors in a standard 65 nm CMOS process.Based on the plasma-wave theory proposed by Dyakonov and Shur,we designed high-responsivity and low-noise multiple detectors for monitoring a pulse-mode 3.0 THz quantum cascade laser(QCL).Furthermore,we present a fully integrated high-speed 32×32-pixel 3.0 THz CMOS image sensor(CIS).The full CIS measures 2.81×5.39 mm^(2) and achieves a 423 V/W responsivity(Rv)and a 5.3 nW integral noise equivalent power(NEP)at room temperature.In experiments,we demonstrate a testing speed reaching 319 fps under continuous-wave(CW)illumina-tion of a 3.0 THz QCL.The results indicate that our terahertz CIS has excellent potential in cost-effective and commercial THz imaging and material detection. | Min Liu Ziteng Cai Jian Liu Nanjian Wu Liyuan Liu | 2023 | Journal of Semiconductors2023，44，10： | 0 |
| 15 | A Low Power Non-Volatile LR-WPAN Baseband Processor with Wake-Up Identification Receiver显示文摘The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power management module.The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique,which increases the robustness and energy efficiency of receiver.The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver.The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode.The baseband processor is designed and verified on a FPGA board.The simulated power consumption of processor is 5.1uW for transmitting and 28.2μW for receiving.The WUI receiver technique reduces the average power consumption of transceiver remarkably.If the transceiver operates 30 seconds in every 15 minutes,the average power consumption of the transceiver can be reduced by two orders of magnitude.The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation. | YU Shuangming FENG Peng WU Nanjian | 2016 | China Communications2016，13，1： | 0 |
| 16 | High power-efficient asynchronous SAR ADC for IoT devices显示文摘This paper presents a power-efficient 100-MS/s,10-bit asynchronous successive approximation register(SAR) ADC.It includes an on-chip reference buffer and the total power dissipation is 6.8 mW.To achieve high performance with high power-efficiency in the proposed ADC,bootstrapped switch,redundancy,set-and-down switching approach,dynamic comparator and dynamic logic techniques are employed.The prototype was fabricated using 65 nm standard CMOS technology.At a 1.2-V supply and 100 MS/s,the ADC achieves an SNDR of 56.2 dB and a SFDR of 65.1 dB.The ADC core consumes only 3.1 mW,resulting in a figure of merit(FOM) of 30.27 fJ/conversionstep and occupies an active area of only 0.009 mm^2. | Beichen Zhang Bingbing Yao Liyuan Liu Jian Liu Nanjian Wu | 2017 | Journal of Semiconductors2017，38，10： | 0 |
| 17 | CMOS image sensors in ISSCC 2023显示文摘In IEEE International Solid-State Circuits Conference(ISSCC)2023,CMOS process is still the dominating fabrication technology for image sensors,and three-dimensional(3D)wafer-stacked process with Cu–Cu pixel-level connection has been adopted to achieve small pixel size and high integration level.The development of CMOS image sensors(CIS)is still focusing on the trends of high performance and more functionalities,such as hybrid event-based vision sensor(EVS)and terahertz(THz)/X-ray image sensor. | Peng Feng Nanjian Wu Jian Liu Liyuan Liu | 2023 | Journal of Semiconductors2023，44，4： | 0 |
| 18 | A fast-locking bang-bang phase-locked loop with adaptive loop gain controller显示文摘This paper proposes a fast-locking bang-bang phase-locked loop(BBPLL). A novel adaptive loop gain controller(ALGC) is proposed to increase the locking speed of the BBPLL. A novel bang-bang phase/frequency detector(BBPFD) with adaptive-mode-selective circuits is proposed to select the locking mode of the BBPLL during the locking process. Based on the detected results of the BBPFD, the ALGC can dynamically adjust the overall gain of the loop for fast-locking procedure. Compared with the conventional BBPFD, only a few gates are added in the proposed BBPFD. Therefore, the proposed BBPFD with adaptive-mode-selective circuits is realized with little area and power penalties. The fast-locking BBPLL is implemented in a 65 nm CMOS technology. The core area of the BBPLL is 0.022 mm^2. Measured results show that the BBPLL operates at a frequency range from0.6 to 2.4 GHz. When operating at 1.8 GHz, the power consumption is 3.1 mW with a 0.9-V supply voltage. With the proposed techniques, the BBPLL achieves a normalized locked time of 1.1μs @ 100 MHz frequency jump.The figure-of-merit of the fast-locking BBPLL is-334 dB. | Jincheng Yang Zhao Zhang Nan Qi Liyuan Liu Jian Liu Nanjian Wu | 2018 | Journal of Semiconductors2018，39，12： | 0 |
| 19 | Subthreshold analog techniques显示文摘IEEE J.Solid-State Circuits,2019,doi:10.1109/JSSC.2018.2889847Low power is a fundamental requirement in state-ofthe-art IC designs,where lower and scalable supply voltagesare demanded due to the power benefits of digital circuits under near-and sub-threshold supply voltages. | Nanjian Wu | 2019 | Journal of Semiconductors2019，40，2： | 0 |
| 20 | Low-cost real-time VLSI system for high-accuracy optical flow estimation using biological motion features and random forests显示文摘This study proposes a low-cost,real-time,very large-scale integration(VLSI)architecture for optical flow estimation.The architecture adopts parallel spatiotemporal filters to extract bio-inspired motion features at each pixel location and uses hardware random forests to infer the motion speed.Our system achieves higher estimation accuracy at low computational hardware costs under real-time constraint than previous biological motion estimation systems. | Cong SHI Junxian HE Shrinivas PUNDLIK Xichuan ZHOU Nanjian WU Gang LUO | 2023 | Science China(Information Sciences)2023，66，5： | 0 |
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